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| rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a adv7172/adv7173 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? analog devices, inc., 2001 digital pal/ntsc video encoder with six dacs (10 bits), color control and enhanced power management features itu-r 1 bt601/656 ycrcb to pal/ntsc video encoder six high quality 10-bit video dacs ssaf? (super sub-alias filter) advanced power management features pc98-compliant (tv detect with polling and auto shutdown to save on power consumption) low power dac mode individual dac on/off control variable dac output current (5 maC36 ma) ultralow sleep mode current hue, brightness, contrast and saturation controls cgms (copy generation management system) wss (wide screen signalling) ntsc-m, pal-m/n, pal-b/d/g/h/i, pal-60 yuv betacam, mii and smpte/ebu n10 output levels single 27 mhz clock required ( 2 oversampling) 80 db video snr 32-bit direct digital synthesizer for color subcarrier multistandard video output support: composite (cvbs) component s-video (y/c) component yuv euroscart rgb component yuv + chroma + luma + cvbs euroscart output rgb + chroma + luma + cvbs programmable clamping output signal advanced programmable power-on reset sequencing video input data port supports: ccir-656 4:2:2 8-bit parallel input format smpte 170m ntsc-compatible composite video itu-r bt.470 pal-compatible composite video luma sharpness control programmable luma filters (low-pass [pal/ntsc], notch [pal/ntsc], extended [ssaf], cif and qcif) programmable chroma filters (low-pass [0.65 mhz, 1.0 mhz, 1.2 mhz and 2.0 mhz], cif and qcif) programmable vbi (vertical blanking interval) programmable subcarrier frequency and phase programmable luma delay ccir and square pixel operation integrated subca rrier locking to external video source color signal control/burst signal control interlaced/noninterlaced operation complete on-chip video timing generator programmable multimode master/slave operation macrovision antitaping rev 7.1 (adv7172 only) 2 closed captioning support teletext insertion port (pal-wst) on-board color bar generation on-board voltage reference 2-wire serial mpu interface (i 2 c ? -compatible and fast i 2 c) single supply 5 v or 3.3 v operation small 48-lead lqfp package applications high performance dvd playback systems, portable video equipment including digital still cameras and laptop pcs, video games, pc video/multimedia and digital satellite/cable systems (set-top boxes/ird) notes 1 itu-r and ccir are used interchangeably in this document (itu-r has replaced ccir recommendations). 2 the macrovision anticopy process is licensed for noncommercial home use only, which is its sole intended use in the device. please contact sales office for latest macrovision version available. ssaf is a trademark of analog devices, inc. i 2 c is a registered trademark of philips corporation. general description the adv7172/adv7173 is an integrated digital video encoder that converts digital ccir-601 4:2:2 8-bit component video data into a standard analog baseband television signal compatible with worldwide standards. there are six dacs available on the adv7172/adv7173. in addition to the composite output signal there is the facility to output s-vhs y/c video, rgb video and yuv video. the on-board ssaf (super sub-alias filter), with extended luminance frequency response and sharp stopband attenuation, enables studio quality video playback on modern tvs, giving optimal horizontal line resolution. an additional sharpness control feature allows extra luminance boost on the frequency response. an advanced power management circuit enables optimal control of power consumption in both normal operating modes and power down or sleep modes. a pc98-compliant autodetect feature has been added to allow the user to determine whether or not the dacs are correctly terminated. if not, the adv7172/ adv7173 flags that they are not connected through the status bit and provides the option of automatically powering them down, thereby reducing power consumption. the adv7172/adv7173 also supports both pal and ntsc square pixel operation. the parts also incorporate wss and cgms-a data control generation.
adv7172/adv7173 #$# functional block diagram 8 8 10-bit dac r set1 comp1 adv7172/adv7173 color data p0 v ref r set2 comp2 p7 dac e dac f dac d dac a dac b dac c brightness and contrast control + add sync + interpolator 10 luma programmable filter + sharpness filter saturation control + add burst + interpolator 10 programmable chroma filter 10 8 8 8 real-time control circuit screset/rtc modulator + hue control 10 10 10 10 10-bit dac 10 10-bit dac 10 m u l t i p l e x e r y u v 8 4:2:2 to 4:4:4 inter- polator 10 10 sin/cos dds block dac control block dac control block 10-bit dac 10 10 10 10 10-bit dac 10 10-bit dac 10 m u l t i p l e x e r yuv to rbg matrix + yuv level control block i 2 c mpu port hsync field/ vsync blank ttx ttxreq v aa reset teletext insertion block ycrcb to yuv matrix clock cso_hso vso clamp sclock sdata alsb video timing generator gnd pal ntsc the adv7172/adv7173 is designed with four color controls (hue, contrast, brightness and saturation). all yuv formats (smpte/ebu n10, mii and betacam) are supported in both pal and ntsc. the output video frames are synchronized with the incoming data timing reference codes. optionally the encoder accepts (and can genera te) hsync vsync #%# adv7172/adv7173 (v aa = 5 v 5% 1 , v ref = 1.235 v, r set1,2 = 600 unless otherwise noted. all specifications t min to t max 2 unless otherwise noted.) parameter test conditions 1 min typ max unit static performance resolution (each dac) 10 bits accuracy (each dac) integral nonlinearity 3 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?in?corresponds to 5 ma output per dac, ?ax?corresponds to 8.66 ma output per dac ) to drive dacs a, b, c, d, e, f. turning off individual dacs reduces i dac correspondingly, also dacs a, b, c can be configured to output a max current of 37 ma but dac d, e, f must be turned off. 9 all six dacs on (dac a, b, c, d, e, f). 10 i cct (circuit current) is the continuous current required to drive the device. 11 only large dacs (dacs a, b, c) on per low power mode. 12 total dac current in sleep mode. 13 total continuous current during sleep mode. specifications subject to change without notice. 5 v specifications specifications #&# adv7172/adv7173especifications parameter test conditions 1 min typ max unit static performance 3 resolution (each dac) 10 bits accuracy (each dac) integral nonlinearity 1.0 lsb differential nonlinearity guaranteed monotonic 1.0 lsb digital inputs 3 input high voltage, v inh 2v input low voltage, v inl 0.8 v input current, i in v in = 0.4 v or 2.4 v ? ? ? ? ? ? ? ? ? ? ? ? ? ?in?corresponds to 5 ma output per dac, ?ax?corresponds to 8.66 ma output per dac ) to drive dacs a, b, c, d, e, f. turning off individual dacs reduces i dac correspondingly, also dacs a, b, c can be configured to output a max current of 37 ma. 9 dacs a, b, c can output 35 ma typically at 3.3 v (r set = 150 ? ? ? ? ? #'# adv7172/adv7173 parameter conditions 1 min typ max unit differential gain 3, 4 normal power mode 0.3 0.7 % differential phase 3, 4 normal power mode 0.4 0.7 degrees differential gain 3, 4 lower power mode 0.5 1.0 % differential phase 3, 4 lower power mode 2.0 3.0 degrees snr 3, 4 (pedestal) rms 75 db rms snr 3, 4 (pedestal) peak periodic 66 db p-p snr 3, 4 (ramp) rms 60 db rms snr 3, 4 (ramp) peak periodic 58 db p-p hue accuracy 3, 4 0.7 degrees color saturation accuracy 3, 4 0.9 % chroma nonlinear gain 3, 4 referenced to 40 ire 1.2 ? ? adv7172/adv7173 #(# 5 v timing specifications (v aa = 5 v 5% 1 , v ref = 1.235 v, r set1 = 600 unless otherwise noted. all specifications t min to t max 2 unless otherwise noted.) parameter conditions min typ max unit mpu port 3, 4 sclock frequency 0 400 khz sclock high pulsewidth, t 1 0.6 reset hsync vsync blank, vso, cso_hso adv7172/adv7173 #)# 3.3 v timing specifications (v aa = 3.0 ve3.6 v 1 , v ref = 1.235 v, r set1,2 = 600 . all specifications t min to t max 2 unless otherwise noted.) parameter conditions min typ max unit mpu port 3, 4 sclock frequency 0 400 khz sclock high pulsewidth, t 1 0.6 reset hsync vsync blank, vso, cso_hso adv7172/adv7173 #*# t 3 t 2 t 6 t 1 t 7 t 5 t 3 t 4 t 8 sdata sclock + , -./. 0 t 9 t 11 clock pixel input data t 10 t 12 hsync , field/ vsync , blank cb y cr y cb y hsync , field/ vsync , blank , cso_hso , vso , clamp t 13 t 14 control i/ps control o/ps + $ .1 2 0 t 16 t 17 ttxreq clock ttx 4 clock cycles 4 clock cycles 4 clock cycles 3 clock cycles 4 clock cycles t 18 + % 0 1 0 dac average current consumption dac d, e, f: the average current consumed by each dac is the dac output current as determined by r set2 /v ref (see appendix 8). dac a, b, c: in normal power mode the average current consumed by each dac is the dac output current as determined by r set1 (see appendix 8). in low power mode the average current consumed by each dac is approximately h alf the dac output current as determined by r set1. consult an-551 for detailed information on adv7172/adv7173 power management. adv7172/adv7173 #3# caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the adv7172/adv7173 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device absolute maximum ratings 1 v aa to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 v voltage on any digital input pin . gnd ?0.5 v to v aa + 0.5 v storage temperature (t s ) . . . . . . . . . . . . . . ?5 j unction temperature = [ v aa ( i dac + i cct ) j a ] 70 c where i dac = 10 ma + (sum of the average currents consumed by each powered-on dac). pin configuration 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 45 44 39 38 37 43 42 41 40 pin 1 identifier top view (not to scale) alsb hsync field/ vsync blank gnd v aa p0 p1 p2 p3 p4 p5 p6 p7 cso hso v aa gnd v aa sclock sdata r set2 adv7172/adv7173 dac f comp1 dac a v aa dac b v aa gnd v aa dac c dac d v aa gnd dac e clock gnd v aa vso reset pal ntsc clamp ttxreq screset/rtc r set1 v ref comp2 gnd ttx ordering guide temperature package package model range description option adv7172kst 0 adv7172/adv7173 #,4# pin function description mnemonic input/output function p7ep0 i 8-bit 4:2:2 multiplexed ycrcb pixel port (p7ep0) p0 represents the lsb. clock i ttl clock input. requires a stable 27 mhz reference clock for standard operation. alter- natively, a 24.5454 mhz (ntsc) or 29.5 mhz (pal) can be used for square pixel operation. hsync hsync vsync vsync blank ? ? vso vso cso_hso cso hso reset adv7172/adv7173 #,,# filter type filter selection passband ripple (db) 3 db bandwidth (mhz) stopband cutoff (mhz) stopband attenuation (db) mr04 0 0 0 0 1 1 1 mr03 0 0 1 1 0 0 1 mr02 0 1 0 1 0 1 0 low-pass (ntsc) low-pass (pal) notch (ntsc) notch (pal) extended (ssaf) cif qcif 0.091 0.15 0.015 0.095 0.051 0.018 monotonic 4.157 4.74 6.54 6.24 6.217 3.0 1.5 7.37 7.96 8.3 8.0 8.0 7.06 7.15 ?6 ?4 ?8 ?6 ?1 ?1 ?0 + & 5 + 6 filter type filter selection passband ripple (db) 3 db bandwidth (mhz) stopband cutoff (mhz) stopband attenuation (db) mr07 0 0 0 0 1 1 1 mr06 0 0 1 1 0 0 1 mr05 0 1 0 1 0 1 0 1.3mhz low pass 0.65mhz low pass 1.0mhz low pass 2.0mhz low pass reserved cif qcif 0.084 monotonic monotonic 0.0645 0.084 monotonic 1.395 0.65 1.0 2.2 0.7 0.5 3.01 3.64 3.73 5.0 3.01 4.08 45 58.5 49 40 45 50 + ' 2 + 6 frequency mhz 0 012 2 magnitude db 46810 10 20 30 50 60 40 70 + ( !0625 7. 5 + frequency mhz 0 012 2 magnitude db 46810 10 20 30 50 60 40 70 + ) .55 7. 5 + internal filter response the y filter supports several different freq uency responses, including two low-pass responses, two notch responses, an extended (ssaf) response with or without gain boost/attenuation, a cif response and a qcif response. the uv filter sup ports several different frequency responses, including four lo w-pass responses, a cif response and a qcif response. t hese can be seen in figures 4 to 18. in extended mode there is the option of twelve responses in the range from e4 db to +4 db. the desired response can be chosen by the user by programming the correct value via the i 2 c. the variation of frequency responses can be seen in figures 19 to 21. ( continued from page 2) adv7172/adv7173 #,$# frequency mhz 0 012 2 magnitude db 46810 10 20 30 50 60 40 70 14 + * !062! 5 + frequency mhz 0 012 2 magnitude db 46810 10 20 30 50 60 40 70 14 + 3 .5! 5 + frequency mhz 0 012 2 magnitude db 46810 10 20 30 50 60 40 70 14 + ,4 1 - 866+95 + frequency mhz 0 012 2 magnitude db 46810 10 20 30 50 60 40 70 14 + ,, 2+5 + frequency mhz 0 012 2 magnitude db 46810 10 20 30 50 60 40 70 14 + ,$ :2+5 + frequency mhz 0 012 2 magnitude db 46810 10 20 30 50 60 40 70 14 + ,% ,%- ;5 7. 2 + adv7172/adv7173 #,%# frequency mhz 0 012 2 magnitude db 46810 10 20 30 50 60 40 70 14 + ,& 4('- ;5 7. 2 + frequency mhz 0 012 2 magnitude db 46810 10 20 30 50 60 40 70 14 + ,' ,4- ;5 7. 2 + frequency mhz 0 012 2 magnitude db 46810 10 20 30 50 60 40 70 14 + ,( $4- ;5 7. 2 + frequency mhz 0 012 2 magnitude db 46810 10 20 30 50 60 40 70 14 + ,) 2+2 + frequency mhz 0 012 2 magnitude db 46810 10 20 30 50 60 40 70 14 + ,* :2+2 + frequency mhz 6 12345 8 7 0 magnitude db 5 15 20 10 25 0 + ,3 1 - 5 + . < ! adv7172/adv7173 #,&# frequency mhz 4 0 6 12345 7 amplitude db 3 1 0 2 3 1 2 + $4 1 - 5 + . < . frequency mhz 4 6 1 magnitude db 2345 2 6 8 10 12 0 2 4 + $, 1 - 5 + . < 2 color bar generation the adv7172/adv7173 can be configured to generate 100/ 7.5/75/7.5 color bars for ntsc or 100/0/75/0 color bars for pal. these are enabled by setting mr46 of mode register 4 to logic 1. square pixel mode the adv7172/adv7173 can be used to operate in square p ixel mode. for ntsc operation, an input clock of 24.5454 mhz is required. alternatively, for pal operation, an input clock of 29.5 mhz is required. the internal timing logic adjusts accord- ingly for square pixel mode operation. color signal control the color information can be switched on and off the video output using bit mr44 of mode register 4. burst signal control the burst information can be switched on and off the video output using bit mr45 of mode register 4. ntsc pedestal control the pedestal on both odd and even fields can be controlled on a line-by-line basis using the ntsc pedestal control registers. this allows the pedestals to be controlled during the v ertical blanking interval. color controls the adv7172/adv7173 allows the user the advantage of control- ling the brightness, contrast, hue and saturation of the color. contrast control contrast adjustment is achieved by scaling the y input data by a factor programmed by the user into the contrast control register bits 5e0. this factor allows the data to be scaled between 75% and 125%. brightness control the brightness is controlled by adding a programmable setup level onto the scaled y data. this brightness level may be added onto the y data in pal mode, ntsc mode without pedestal or ntsc mode with pedestal, in which case it is added directly onto the 7.5 ire pedestal already present. the level added is programmed by the user into the brightness control register (bits 4e0) and the user is capable of adding from 0 ire to a maximum of 14 ire in 32 (2 5 ) steps. because of different gains in the datapath for each mode, different values may need to be programmed to obtain the same ire setup level in each mode. maximum brightness is achieved when 31 is programmed into the brightness control register. table i illus- trates the maximum setup/brightness amplitudes available in the various modes. note that if a level of less than 7.5 ire is required on the y data in ntsc mode, then ntsc without pedestal must be the mode selected. table i. maximum brightness levels available brightness control mode register setup ntsc no pedestal 00011111 14 ire ntsc pedestal 00011111 13 ire pal 00011111 99 mv color saturation control color adjustment is achieved by scaling the cr and cb input data by a factor programmed by the user into the color control registers 1 and 2, bits 5e0. this factor allows the data to be scaled between 75% and 125%. hue control the hue adjustment is achieved on the composite and chroma outputs by adding a phase offset onto the color subcarrier in the active video but leaving the color burst unmodified, i.e., only the phase between the video and the color burst is modified and hence the hue is shifted. hue adjustment is under the con- trol of the hue control register. the adv7172/adv7173 provides a range of adv7172/adv7173 #,'# yuv levels this functionality is under the control of mode register 5, bits 2e0. bit 0 (mr50) allows the adv7172/adv7173 to output smpte lev els on the y output when configured in ntsc m ode, and betacam levels on the y output when configured in pal mode and vice-versa. video sync betacam 286 mv 714 mv smpte 300 mv 700 mv mii 300 mv 700 mv as the datapath is branched at the output of the filters, the luma signal relating to the cvbs or s-video y/c output is unaltered. only the y output of the yuv outputs is scaled. bits 2e1 (mr52emr51) allow uv levels to have a peak-peak amplitude of 700 mv or 1000 mv, or the default values of 934 mv in ntsc and 700 mv in pal. autodetect control the adv7172/adv7173 provides the option of automatically powering down the dacs a, b and c if they are not correctly terminated (i.e., the 75 ? ? ? ? ? ? sync blank vsync adv7172/adv7173 #,(# h/ltransition count start low 128 rtc time slot: 01 14 67 68 not used in adv7172/adv7173 19 valid sample invalid sample fscpll increment 1 8/llc 5 bits reserved sequence bit 2 reset bit 3 reserved 4 bits reserved 21 0 13 14 bits reserved 0 notes 1 f sc pll increment is 22 bits long, value loaded into adv7172/adv7173 fsc dds register is f sc pll increment bits 21:0 plus bits 0:9 of subcarrier frequency registers. all zeros should be written to the subcarrier frequency registers of the adv7172/adv7173. 2 sequence bit pal: 0 = line normal, 1 = line inverted ntsc: 0 = no change 3 reset bit reset adv7172/adv7173 s dds composite video e.g., vcr or cable hsync field/ vsync clock green/composite/y red/chroma/v blue/luma/u green/composite/y blue/luma/u red/chroma/v adv7172/adv7173 p7 p0 screset/rtc video decoder adv7185 lcc1 gll p19-p12 + $$ 020 2 mode 0 (ccire656): slave option (timing register 0 tr0 = x x x x x 0 0 0) the adv7172/adv7173 is controlled by the sav (start active video) and eav (end active video) time codes in the pixel data. all timing information is transmitted using a 4-byte synchronization pattern. a synchronization pattern is sent immediately bef ore and after each line during active picture and retrace. mode 0 is illustrated in figure 23. the hsync vsync blank y c r y f f 0 0 0 0 x y 8 0 1 0 8 0 1 0 f f 0 0 f f a b a b a b 8 0 1 0 8 0 1 0 f f 0 0 0 0 x y c b y c r c b y c b y c r eav code sav code ancillary data (hanc) 4 clock 4 clock 268 clock 1440 clock 4 clock 4 clock 280 clock 1440 clock end of active video line start of active video line analog video input pixels ntsc/pal m system (525 llnes/60hz) pal system (625 lines/50hz) y + $% 0 - 486 - 9 adv7172/adv7173 #,)# mode 0 (ccire656): master option (timing register 0 tr0 = x x x x x 0 0 1) the adv7172/adv7173 generates h, v, and f signals required for the sav (start active video) and eav (end active video) time codes in the ccir656 standard. the h bit is output on the hsync blank vsync 522 523 524 525 1 2 3 4 5 67 8 9 10 11 20 21 22 display display vertical blank odd field even field h v f 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285 odd field even field display display vertical blank h v f + $& 0 - 48!062- - 9 622 623 624 625 1 2 3 4 5 67 21 22 23 display display vertical blank h v f odd field even field 309 310 311 312 314 315 316 317 318 319 320 334 335 336 display display vertical blank h v f odd field even field 313 + $' 0 - 48.5- - 9 adv7172/adv7173 #,*# analog video h f v + $( 0 - 4 0 8- - 9 mode 1: slave option hsync blank hsync blank blank 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285 odd field even field display display vertical blank hsync blank field 522 523 524 525 1234 5 6 78 9 10 11 20 21 22 display display vertical blank odd field even field blank field hsync owk_n orob_a__ adv7172/adv7173 #,3# 622 623 624 625 1 2 3 4 5 6 7 21 22 23 display vertical blank odd field even field hsync blank field display 309 310 311 312 313 314 315 316 317 318 319 334 335 336 display vertical blank odd field even field hsync blank field display 320 + $* 0 - ,8.59 mode 1: master option hsync blank hsync blank blank hsync blank field pixel data pal = 12 clock/2 ntsc = 16 clock/2 pal = 132 clock/2 ntsc = 122 clock/2 cb y cr y hsync blank owk_n orob_a__sb_o_kebotoab_etke adv7172/adv7173 #$4# mode 2: slave option hsync vsync blank hsync vsync vsync hsync blank blank 522 523 524 525 1234 5 678 9 10 11 20 21 22 display display vertical blank odd field even field hsync blank vsync 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285 odd field even field display display vertical blank hsync blank vsync owk_n orob_a__ 6226236246251234 5 67 21 22 23 display vertical blank odd field even field hsync blank vsync display 309 310 311 312 313 314 315 316 317 318 319 334 335 336 display vertical blank odd field even field hsync blank display 320 vsync owk_n orob_a__ adv7172/adv7173 #$,# mode 2: master option hsync vsync blank hsync vsync vsync hsync blank blank hsync blank vsync hsync blank vsync pal = 12 clock/2 ntsc = 16 clock/2 hsync vsync blank pixel data pal = 132 clock/2 ntsc = 122 clock/2 cb y cr y + %$ 0 - $7 7=+0 - >6 pal = 864 clock/2 ntsc = 858 clock/2 pal = 132 clock/2 ntsc = 122 clock/2 hsync vsync blank pixel data pal = 12 clock/2 ntsc = 16 clock/2 cb y cr y cb + %% 0 - $=7 7+0 - >6 adv7172/adv7173 #$$# mode 3: master/slave option hsync blank hsync blank blank 522 523 524 525 1 2 3 4 5 67 8 9 1011 202122 display display vertical blank odd field even field blank field 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285 even field display display vertical blank hsync odd field blank field hsync owk_n orob_a__ 622 623 624 625 1 2 3 4 5 6 7 21 22 23 display display vertical blank odd field even field blank field 309 310 311 312 314 315 316 317 318 319 320 334 335 336 display display vertical blank odd field even field 313 hsync blank field hsync owk_n orob_a__ adv7172/adv7173 #$%# power-on reset after power-up, it is necessary to execute a reset operation. a reset occurs on the falling edge of a high-to-low transition on the reset reset reset xxxxxxx xxxxxxx xxxxxxx xxxxxxx digital timing signals suppressed black value black value with sync valid video valid video 0 1 timing active reset composite/y chroma mr26 pixel data valid digital timing 0 512 + %( reset hh adv7172/adv7173 #$&# cso hso vso cso hso vso hso cso mr57 = 1 mr57 = 0 0h + %* 2 = 0 mpu port description the adv7172 and adv7173 support a 2-wire serial (i 2 c- compatible) microprocessor bus driving multiple peripherals. two inputs serial data (sdata) and serial clock (sclock) carry information between any device connected to the bus. each slave device is recognized by a unique address. the adv7172 and adv7173 each have four possible slave addresses for b oth read and write operations. these are unique addresses for each device and are illustrated in figure 39 and figure 40. the lsb sets either a read or write operation. l ogic level 1 corresponds to a read operation while logic level 0 corresponds to a write operation. a1 is set by setting the alsb pin of the adv7172/adv7173 to logic level 0 or logic level 1. when alsb is set to 0, there is greater bandwidth on the i 2 c lines, which allows high-speed data transfers on this bus. when alsb is set to 1, there is reduced input band- width on the i 2 c lines, which means that impulses of less than 50 ns w ill not pass into the i 2 c internal controller. this mode is recommended for noisy systems. address control set up by alsb read/write control 0 write 1 read 1 1 0 1 0 1 a1 x + %3 ),)$6 address control set up by alsb read/write control 0 write 1 read 0 1 0 1 0 1 a1 x + &4 ),)%6 to control the various devices on the bus the following protocol must be followed. first the master initiates a data transfer by establishing a start condition, defined by a high-to-low transition on sdata while sclock remains high. this indicates that an address/data stream will follow. all peripherals respond to the start condition and shift the next eight bits (7-bit address + r/ w w vso hso cso output video 52512345678910 11-19 example: ntsc + %) cso hso vso h adv7172/adv7173 #$'# the adv7172/adv7173 acts as a standard slave device on the bus. the data on the sdata pin is eight bits long, supporting the 7-bit addresses plus the r/ w 1-7 8 9 1-7 8 9 1-7 8 9 p s start addr r/ w ack subaddress ack data ack stop sdata sclock + &, 0 figure 42 shows bus write and read sequences. register accesses the mpu can write to or read from all of the registers of the adv7172/adv7173 except the subaddress register, which is a write-only register. the subaddress register determines which register the next read or write operation accesses. all communi- cations with the part through the bus start with an access to the subaddress register. a read/write operation is then performed from/to the target address, which then increments to the next address until a stop command on the bus is performed. register programming the following section describes each register, including subaddress register, mode registers, subcarrier frequency registers, subcar- rier phase register, timing registers, closed captioning extended data registers, closed captioning data registers, ntsc pedestal control/pal teletext control registers, cgms/wss registers, contrast register, u- or v-scale registers, hue adjust register, brightness control register and sharpness control register in terms of its configuration. all registers can be read from as well as written to. data a(s) s slave addr a(s) sub addr a(s) lsb = 0 lsb = 1 data a (s) p s slave addr a(s) sub addr a(s) s slave addr a(s) data a (m ) data p write sequence read sequence a (s) = no-acknowledge by slave a (m) = no-acknowledge by master a(s) = acknowledge by slave a(m) = acknowledge by master s = start bit p = stop bit a(m) + &$ @ 6? adv7172/adv7173 #$(# subaddress register (sr7esr0) the communications register is an 8-bit write-only register. after the part has been accessed over the bus and a read/write opera- tion is selected, the subaddress is set up. the subaddress register determines to/from which register the operation takes place. figure 43 shows the various operations under the control of the subaddress register. 0 should always be written to sr7. register select (sr6esr0) these bits are set up to point to the required starting address. sr3 sr2 sr1 sr0 sr7 sr6 sr5 zero should be written here sr7 sr4 adv7172/73 subaddress register address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1ah 1bh 1ch 1dh 1eh 1fh 20h 21h 22h 23h 24h ... ... ... 3ah 3bh 3ch 3dh 3eh 3fh 40h 41h 42h 43h 44h 45h 46h 47h 48h 49h 4ah 4bh sr6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 . . . 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 sr5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 . . . 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 sr4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 . . . 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 sr3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 . . . 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 . . . 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 . . . 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 . . . 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 mode register 0 mode register 1 mode register 2 mode register 3 mode register 4 mode register 5 mode register 6 mode register 7 reserved reserved timing register 0 timing register 1 sub carrier frequency register 0 sub carrier frequency register 1 sub carrier frequency register 2 sub carrier frequency register 3 sub carrier phase register closed captioning extended data byte 0 closed captioning extended data byte 1 closed captioning data byte 0 closed captioning data byte 1 ntsc pedestal/teletext control register 0 ntsc pedestal/teletext control register 1 ntsc pedestal/teletext control register 2 ntsc pedestal/teletext control register 3 cgms/wss 0 cgms/wss 1 cgms/wss 2 teletext request control register contrast control register u scale register v scale register hue adjust register brightness control register sharpness control register reserved .... .... .... .... macrovision register [adv7172 only] macrovision register [adv7172 only] macrovision register [adv7172 only] macrovision register [adv7172 only] macrovision register [adv7172 only] macrovision register [adv7172 only] macrovision register [adv7172 only] macrovision register [adv7172 only] macrovision register [adv7172 only] macrovision register [adv7172 only] macrovision register [adv7172 only] macrovision register [adv7172 only] macrovision register [adv7172 only] macrovision register [adv7172 only] macrovision register [adv7172 only] macrovision register [adv7172 only] macrovision register [adv7172 only] macrovision register [adv7172 only] sr2 sr1 sr0 + &% 6 adv7172/adv7173 #$)# mode register 0 mr0 (mr07emr00) (address (sr4esr0) = 00h) figure 44 shows the various operations under the control of mode register 0. mr0 bit description output video standard selection (mr01emr00) these bits are used to set up the encoder mode. the adv7172/ adv7173 can be set up to output ntsc, pal (b, d, g, h, i), pal m or pal n standard video. luma filter select (mr02emr04) these bits specify which luma filter is to be selected. the filter selection is made independent of whether pal or ntsc is selected. chroma filter select (mr05emr07) these bits select the chroma filter. a low-pass filter can be selected with a choice of cutoff frequencies (0.65 mhz, 1.0 mhz, 1.3 mhz, or 2 mhz), along with a choice of cif or qcif filters. mode register 1 mr1 (mr17emr10) (address (sr4esr0) = 01h) figure 45 shows the various operations under the control of mode register 1. mr1 bit description dac control (mr15emr10) mr15emr10 bits can be used to power down the dacs. this can be used to reduce the power consumption of the adv7172/ adv7173 if any of the dacs are not required in the application. low power mode control (mr16) this bit enables the lower power mode of the adv7172/ adv7173. t his will reduce by approximately 50% the average supply current consumed by each large dac which is powered on. for each dac in low power mode, the relationship between r set1 /v ref and the output current is unchanged by this (see appendix 8). this bit is only relevant to the larger dacs, dacs a, b, and c. dacs d, e, and f are not affected by this low power mode. reserved (mr17) a logic 0 must be written to this bit. chroma filter select mr07 mr06 0 0 0 1.3mhz low-pass filter 0 0 1 0.65mhz low-pass filter 0 1 0 1.0mhz low-pass filter 0 1 1 2.0mhz low-pass filter 1 0 0 reserved 1 0 1 cif 1 1 0 qcif 1 1 1 reserved mr05 mr01 mr00 mr07 mr02 mr03 mr05 mr06 mr04 output video standard selection mr01 mr00 0 0 ntsc 0 1 pal (b, d, g, h, i) 1 0 pal (m) 1 1 pal (n) luma filter select mr04 mr03 0 0 0 low-pass filter (ntsc) 0 0 1 low-pass filter (pal) 0 1 0 notch filter (ntsc) 0 0 1 notch filter (pal) 1 0 0 extended mode 1 0 1 cif 1 1 0 qcif 1 1 1 reserved mr02 + && - 48-49 mr11 mr10 mr17 mr12 mr13 mr15 mr16 mr14 low power mode control 0 disable 1 enable mr16 mr14 dac a dac c control mr15 mr17 zero should be written to this bit 0 power-down 1 normal 0 power-down 1 normal dac b dac c control dac c dac c control mr13 0 power-down 1 normal dac e dac c control mr11 0 power-down 1 normal mr12 0 power-down 1 normal dac d dac c control dac f dac c control mr10 0 power-down 1 normal + &' - ,8-,9 adv7172/adv7173 #$*# mode register 2 mr2 (mr27emr20) (address (sr4esr0) = 02h) mode register 2 is an 8-bit-wide register. figure 46 shows the various operations under the control of mode register 2. mr2 bit description rgb/yuv control (mr20) this bit enables the output from the dacs to be set to yuv or rgb output video standard. large dacs control (mr21) this bit controls the output from dacs a, b, and c. when this bit is set to 1, composite, luma, and chroma signals are output from dacs a, b, and c (respectively). when this bit is set to 0, rgb or yuv may be output from these dacs. scart enable control (mr22) this bit is used to switch the dac outputs from scart to a euroscart configuration. a complete table of all dac output configurations is shown in table ii. pedestal control (mr23) this bit specifies whether a pede stal is to be generated on the ntsc composite video signal. this bit is invalid in the pal mode. square pixel control (mr24) this bit is used to set up square pixel mode. this is available in slave mode only. for ntsc, a 24.54 mhz clock must be supplied. for pal, a 29.5 mhz clock must be supplied. standard i 2 c control (mr25) this bit controls the video standard used by the adv7172/ adv7173. when this bit is set to 1, the video standard bits programmed in mode register 0, bits 0e1, indicate the video standard. when this bit is set to 0, the adv7172/adv7173 is forced into the standard selected by the ntsc_pal pin. pixel data valid control (mr26) after reset, this bit has the value 0 and the pixel data input to the encoder is blanked such that a black screen is output from the dacs. the adv7172/adv7173 will be set to master mode timing. when this bit is set to 1 by the user (via the i 2 c), pixel data passes to the pins and the encoder reverts to the timing mode defined by timing mode register 0. sleep mode control (mr27) when this bit is set (1), sleep mode is enabled. with this mode enabled the adv7172/adv7173 power consumption is reduced to less than 20 mr21 mr27 mr22 mr23 mr26 mr25 mr24 mr20 sleep mode control 0 disable 1 enable mr27 standard i 2 c control 0 disable 1 enable mr25 pixel data valid control 0 disable 1 enable mr26 square pixel control 0 disable 1 enable mr24 scart enable control 0 disable 1 enable mr22 rgb/yuv control 0 rgb output 1 yuv output mr20 pedestal control 0 pedestal on 1 pedestal off mr23 large dacs control 0 rgb/yuv/comp 1 comp/luma/chroma mr21 + &( - $8-$9 table ii. dac output configuration matrix mr22 mr21 mr20 dac a dac b dac c dac d dac e dac f 0 0 0 g b r cvbs luma chroma 0 0 1 y u v cvbs luma chroma 0 1 0 cvbs luma chroma g b r 0 1 1 cvbs luma chroma y u v 1 0 0 cvbs b r g luma chroma 1 0 1 cvbs u v y luma chroma 1 1 0 cvbs luma chroma g b r 1 1 1 cvbs luma chroma y u v adv7172/adv7173 #$3# mr31 mr30 mr37 mr32 mr34 mr33 mr35 mr36 mr31 mr30 reserved for revision code vbi open 0 disable 1 enable mr32 ttxrq bit mode control 0 disable 1 enable mr34 teletext enable 0 disable 1 enable mr33 active video filter 0 enable 1 disable mr37 closed captioning field selection 0 0 no data out 0 1 odd field only 1 0 even field only 1 1 data out (both fields) mr36 mr35 + &) - %8-%9 mode register 3 mr3 (mr37emr30) (address (sr4esr0) = 03h) mode register 3 is an 8-bit-wide register. figure 47 shows the various operations under the control of mode register 3. mr3 bit description revision code (mr31emr30) this bit is read-only and indicates the revision of the device. vbi_open (mr32) this bit determines whether or not data in the vertical blank- ing interval (vbi) is output to the analog outputs or blanked. vbi_open is available in all timing modes. also, if both blank adv7172/adv7173 #%4# mode register 4 mr4 (mr47emr40) (address (sr4esr0) = 04h) mode register 4 is a 8-bit wide register. figure 48 shows the various operations under the control of mode register 4. mr4 bit description vsync vsync vsync vsync hsync blank mr41 mr40 mr47 mr42 mr44 mr43 mr45 mr46 chrominance control 0 enable color 1 disable color mr44 color bar control 0 disable 1 enable mr46 vsync 3h 0 disable 1 enable mr40 interlaced mode control 0 interlaced 1 noninterlaced mr47 burst control 0 enable burst 1 disable burst mr45 active video line duration 0 720 pixels 1 710/702 pixels mr43 genlock selection x 0 disable genlock 0 1 enable subcarrier reset pin 1 1 enable rtc pin mr42 mr41 + &* - &8-&9 adv7172/adv7173 #%,# mode register 5 mr5 (mr57emr50) (address (sr4-sr0) = 05h) mode register 5 is an 8-bit-wide register. figure 49 shows the various operations under the control of mode register 5. mr5 bit description y-level control (mr50) this bit controls the y output level on the adv7172/adv7173. if this bit is set (0), the encoder outputs smpte levels when configured in pal mode and betacam levels when configured in ntsc mode. if this bit is set (1), the encoder outputs betacam levels when configured in pal mode and smpte levels when configured in ntsc mode. uv-levels control (mr52emr51) these bits control the u and v output levels on the adv7172/ adv7173. it is possible to have uv levels with a peak-peak amplitude of either 700 mv (mr52 + mr51 = 01) or 1000 mv (mr52 + mr51 = 10) in ntsc and pal. it is also possible to have default values of 934 mv for ntsc and 700 mv for pal (mr52 + mr51 = 00). rgb sync (mr53) this bit is used to set up the rgb outputs with the sync infor- mation encoded on all rgb outputs. clamp delay (mr55emr54) these bits control the delay or advance of the clamp signal in the front or back porch of the adv7172/ad v7173. it is p ossible to delay or advance the pulse by 0, 1, 2 or 3 clock cycles. clamp delay direction (mr56) this bit controls a positive or negative delay in the clamp signal. if this bit is set (1), the delay is negative. if it is not set (0), the delay is positive. clamp position (mr57) this bit controls the position of the clamp signal. if this bit is set (1), the clamp signal is located in the back porch posi- tion. if this bit is set to (0), the clamp signal is located in the front porch position. mr51 mr50 mr57 mr52 mr54 mr53 mr55 mr56 clamp delay direction 0 positive 1 negative mr56 clamp position 0 front porch 1 back porch mr57 clamp delay 0 0 no delay 011 pclk 102 pclk 113 pclk mr55 mr54 uv-levels control 0 0 default levels 0 1 700mv 1 0 1000mv 1 1 reserved mr52 mr51 rgb sync 0 disable 1 enable mr53 y-level control 0 disable 1 enable mr50 + &3 - '8-'9 adv7172/adv7173 #%$# mode register 6 mr6 (mr67emr60) (address (sr4esr0) = 06h) mode register 6 is an 8-bit-wide register. figure 50 shows the various operations under the control of mode register 6. mr6 bit description power-up sleep mode control (mr60) after reset this bit is set to 0, if both screset/rtc and ntsc_pal pins are tied high, the part will power-up in sleep mode (to facilitate low power consumption before the i 2 c is initialized). when this bit is set to 1 (via the i 2 c), sleep mode control passes to mode register 2, bit 7. reserved (mr61) a logic 0 must be written to this bit. luma autodetect control (mr62) this bit controls which mode of autodetect operation is being used on the luma dac (dac b) on the adv7172/adv7173. if this bit is set (0), mode 0 is on; if this bit is set (1), then mode 1 is being used. composite autodetect control (mr63) this bit controls which mode of autodetect operation is being used on the composite dac (dac a) on the adv7172/ adv7173. if this bit is set (0), mode 0 is on; if this bit is set (1), then mode 1 is being used. dac termination control (mr64) this bit controls the load termination resistance detected by the autodetect functionality. if this bit is set (0), the autodetect feature is used to determine if a 75 ? ? mr61 mr60 mr67 mr62 mr64 mr63 mr65 mr66 composite dac status bit 0 not terminated 1 terminated mr67 dac termination control 01 mode 12 mode mr64 luma dac status bit 0 not terminated 1 terminated mr66 comp autodetect control 0 mode 0 1 mode 1 mr63 luma autodetect control 0 mode 0 1 mode 1 mr62 mr61 zero should be written to this bit power-up sleep mode control 0 enable 1 disable mr60 zero should be written to this bit mr65 + '4 - (8-(9 adv7172/adv7173 #%%# mode register 7 mr7 (mr77emr70) (address (sr4esr0) = 07h) mode register 7 is an 8-bit-wide register. figure 51 shows the various operations under the control of mode register 7. mr7 bit description color control enable (mr70) this bit is used to enable control of contrast and saturation of color. if this bit is set (1), color controls are enabled; if this bit is set (0), the color control features are disabled. luma saturation control (mr71) when this bit is set (1), the luma signal will be clipped if it reaches a limit that corresponds to an input luma value of 255 after scaling by the contrast control. this prevents the chrominance component of the composite video signal being clipped if the amplitude of the luma is too high. when this bit is set (0), this control is disabled. hue adjust enable (mr72) this bit is used to enable hue adjustment on the composite and chroma output signals of the adv7172/adv7173. when this bit is set (1), the hue of the color is adjusted by the phase offset described in the hue control register. when this bit is set (0) hue adjustment is disabled. brightness enable control (mr73) this bit is used to enable brightness control on the adv7172/ adv7173 by enabling the programmable setup level or ped- estal described in the brightness control register to be added to the scaled y data. when this bit is set (1), brightness control is enabled. when this bit is set (0), brightness control is disabled. sharpness response enable (mr74) this bit is used to enable the sharpness of the luminance signal on the adv7172/adv7173 (mr04emr02 = 100). the various responses of the filter are determined by the sharpness re sponse register. when this bit is set (1) the luma response is altered by the amount described in the sharpness response register. when this bit is set (0), the sharpness control is disabled (see figures 19, 20, and 21 for luma signal responses). cso_hso hso cso cso_hso cso hso mr71 mr70 mr77 mr72 mr74 mr73 mr75 mr76 mr77 mr76 zero should be written to these bits cso_hso output control 0 hso out 1 cso out mr75 brightness enable control 0 disable 1 enable mr73 luma saturation control 0 disable 1 enable mr71 sharpness response enable 0 disable 1 enable mr74 hue adjust enable 0 disable 1 enable mr72 color control enable 0 disable 1 enable mr70 + ', - )8-)9 adv7172/adv7173 #%&# timing register 0 (tr07etr00) (address (sr4esr0) = 0ah) figure 52 shows the various operations under the control of timing register 0. this register can be read from as well as written to. tr0 bit description master/slave control (tr00) this bit controls whether the adv7172/adv7173 is in master or slave mode. timing mode selection (tr02etr01) these bits control the timing mode of the adv7172/adv7173. these modes are described in more detail in the timing and control section of the data sheet. blank blank blank tr01 tr00 tr07 tr02 tr03 tr05 tr06 tr04 timing register reset tr07 blank input control 0 enable 1 disable tr03 master/slave control 0 slave timing 1 master timing tr00 luma delay 0 0 0ns delay 0 1 74ns delay 1 0 148ns delay 1 1 222ns delay tr05 tr04 timing mode selection 0 0 mode 0 0 1 mode 1 1 0 mode 2 1 1 mode 3 tr02 tr01 min luma value 0 luma min = sync bottom 1 luma min = blank 7.5 ire tr06 + '$ 0 4 adv7172/adv7173 #%'# timing register 1 (tr17etr10) (address (sr4esr0) = 0bh) timing register 1 is an 8-bit-wide register. figure 53 shows the various operations under the control of timing register 1. this register can be read from as well writ- ten to. this register can be used to adjust the width and position of the master mode timing signals. tr1 bit description hsync hsync hsync vsync hsync vsync hsync hsync vsync vsync hsync hsync tr11 tr10 tr17 tr12 tr13 tr15 tr16 tr14 hsync to pixel data adjust tr17 tr16 000 t pclk 011 t pclk 102 t pclk 113 t pclk hsync to field/ vsync delay tr13 tr12 000 t pclk 014 t pclk 108 t pclk 1 1 16 t pclk t b hsync width 001 t pclk 014 t pclk 1 0 16 t pclk 1 1 128 t pclk tr11 tr10 t a hsync to field rising edge delay (mode 1 only) x0t b x1t b + 32 s tr15 tr14 t c vsync width (mode 2 only) 001 t pclk 014 t pclk 1 0 16 t pclk 1 1 128 t pclk line 313 line 314 line 1 t b timing mode 1 (master/pal) hsync field/ vsync t a t c tr15 tr14 + '% 0 , adv7172/adv7173 #%(# subcarrier frequency registers 3e0 (fsc3efsc0) (address (sr4esr0) = 0che0fh) these 8-bit-wide registers are used to set up the subcarrier frequency. the value of these registers is calculated by using the following equation: subcarrier frequency gister f f clk scf re = 2 32 e1 f clk = 27 mhz, f scf = 3.5795454 mhz subcarrier frequencyvalue = 2 32 e . 1 27 10 3 579454 10 6 6 f 07 c 16 hex figure 54 shows how the frequency is set up by the four registers. subcarrier phase register (fp7efp0) (address (sr4esr0) = 10h) this 8-bit-wide register is used to set up the subcarrier phase. each bit represents 1.41 subcarrier frequency reg 3 subcarrier frequency reg 2 subcarrier frequency reg 1 subcarrier frequency reg 0 fsc30 fsc29 fsc27 fsc25 fsc28 fsc24 fsc31 fsc26 fsc22 fsc21 fsc19 fsc17 fsc20 fsc16 fsc23 fsc18 fsc14 fsc13 fsc11 fsc9 fsc12 fsc8 fsc15 fsc10 fsc6 fsc5 fsc3 fsc1 fsc4 fsc0 fsc7 fsc2 + '& 6 + ? closed captioning even field data register 1e0 (ced15eced0) (address (sr4esr0) = 11e12h) these 8-bit wide registers are used to set up the closed captioning extended data bytes on even fields. figure 55 shows how the high and low bytes are set up in the registers. byte 1 byte 0 ced6 ced5 ced3 ced1 ced4 ced0 ced7 ced2 ced14 ced13 ced11 ced9 ced12 ced8 ced15 ced10 + '' 2 2 1 closed captioning odd field data register 1e0 (ccd15eccd00) (subaddress (sr4esr0) = 13e14h) these 8-bit-wide registers are used to set up the closed captioning data bytes on odd fields. figure 56 shows how the high and low bytes are set up in the registers. byte 1 ccd14 ccd13 ccd11 ccd9 ccd12 ccd8 ccd15 ccd10 byte 0 ccd6 ccd5 ccd3 ccd1 ccd4 ccd0 ccd7 ccd2 + '( 2 2 ntsc pedestal/pal teletext control registers 3e0 (pce15e0, pco15e0)/(txe15e0, txo15e0) (subaddress (sr4esr0) = 15e18h) these 8-bit-wide registers are used to enable the ntsc pedes- tal/pal teletext on a line-by-line basis in the vertical blanking interval for both odd and even fields. figures 57 and 58 show the f our control registers. a logic 1 in any of the bits of these registers has the effect of turn ing the pedestal off on the equivalent line when used in ntsc. a logic 1 in any of the bits of these registers has the effect of turning teletext on on the equivalent line when used in pal. field 1/3 line 17 line 16 line 15 line 14 line 13 line 12 line 11 line 10 pco6 pco5 pco3 pco1 pco4 pco0 pco7 pco2 field 1/3 line 25 line 24 line 23 line 22 line 21 line 20 line 19 line 18 pco14 pco13 pco11 pco9 pco12 pco8 pco15 pco10 field 2/4 line 17 line 16 line 15 line 14 line 13 line 12 line 11 line 10 pce6 pce5 pce3 pce1 pce4 pce0 pce7 pce2 field 2/4 line 25 line 24 line 23 line 22 line 21 line 20 line 19 line 18 pce14 pce13 pce11 pce9 pce12 pce8 pce15 pce10 + ') . 2 field 2/4 line 22 line 21 line 20 line 19 line 18 line 17 line 16 line 15 txe14 txe13 txe11 txe9 txe12 txe8 txe15 txe10 field 1/3 line 14 line 13 line 12 line 11 line 10 line 9 line 8 line 7 txo6 txo5 txo3 txo1 txo4 txo0 txo7 txo2 field 1/3 line 22 line 21 line 20 line 19 line 18 line 17 line 16 line 15 txo14 txo13 txo11 txo9 txo12 txo8 txo15 txo10 field 2/4 line 14 line 13 line 12 line 11 line 10 line 9 line 8 line 7 txe6 txe5 txe3 txe1 txe4 txe0 txe7 txe2 + '* 0 1 2 adv7172/adv7173 #%)# teletext request control register tc07 (tc07etc00) (address (sr4esr0) = 1ch) teletext control register is an 8-bit-wide register. see figure 59. ttxreq rising edge control (tc07etc04) these bits control the position of the rising edge of ttxreq. it can be programmed from zero clock cycles to a max of 15 clock cycles. ttxreq falling edge control (tc03etc00) these bits control the position of the falling edge of ttxreq. it can be programmed from zero clock cycles to a max of 15 clock cycles. this controls the active window for teletext data. increasing this value reduces the amount of teletext bits below the default of 360. if bits tc03etc00 are 00hex when bits tc07etc04 are changed, then the falling edge of ttxreq will track that of the rising edge (i.e., the time between the fall- ing and rising edge remains constant). cgms_wss register 0 c/w0 (c/w07ec/w00) (address (sr4esr0) = 19h) cgms_wss register 0 is an 8-bit-wide register. figure 60 shows the operations under control of this register. c/w bit description cgms data (c/w03ec/w00) these four data bits are the final four bits of cgms data out- put stream. note it is cgms data only in these bit positions i.e., wss data does not share this location. cgms crc check control (c/w04) when this bit is enabled (1), the last six bits of the cgms data, i.e., the crc check sequence, are calculated internally by the adv7172/adv7173. if this bit is disabled (0), the crc values in the register are output to the cgms data stream. cgms odd field control (c/w05) when this bit is set (1), cgms is enabled for odd fields. note that this is only valid in ntsc mode. cgms even field control (c/w06) when this bit is set (1), cgms is enabled for even fields. note that this is only valid in ntsc mode. wide screen signal control (c/w07) when this bit is set (1), wide screen signalling is enabled. note that this is only valid in pal mode. tc01 tc00 tc07 tc02 tc04 tc03 tc05 tc06 ttxreq rising edge control tc07 tc06 tc05 tc04 0 0 0 0 0 pclk 0 0 0 1 1 pclk " " " " " pclk 1 1 1 0 14 pclk 1 1 1 1 15 pclk ttxreq falling edge control tc03 tc02 tc01 tc00 0 0 0 0 0 pclk 0 0 0 1 1 pclk " " " " " pclk 1 1 1 0 14 pclk 1 1 1 1 15 pclk + '3 0 1 ? 2 cgms crc check control 0 disable 1 enable c/w04 wide screen signal control 0 disable 1 enable c/w07 c/w07 c/w06 c/w05 c/w04 c/w03 c/w02 c/w01 c/w00 cgms odd field control 0 disable 1 enable c/w05 c/w03 c/w00 cgms data cgms even field control 0 disable 1 enable c/w06 + (4 2<-6a@66 4 adv7172/adv7173 #%*# cgms_wss register 1 c/w1 (c/w17ec/w10) (address (sr4esr0) = 1ah) cgms_wss register 1 is an 8-bit-wide register. figure 61 shows the operations under control of this register. c/w1 bit description cgms/wss data (c/w15ec/w10) these bit locations are shared by cgms data and wss data. in ntsc mode these bits are cgms data. in pal mode these bits are wss data. cgms data only (c/w17ec/w16) these bits are cgms data bits only. cgms_wss register 2 c/w1(c/w27ec/w20) (address (sr4-sr0) = 1bh) cgms_wss register 2 is an 8-bit-wide register. figure 62 shows the operations under control of this register. c/s bit description cgms/wss data (c/w27ec/w20) these bit locations are shared by cgms data and wss data. in ntsc mode these bits are cgms data. in pal mode these bits are wss data. contrast control register (cc07ecc00) (address (sr4esr0) = 1dh) the contrast control register is an 8-bit-wide register used to scale the y output levels. figure 63 shows the operations under control of this register. cc0 bit description reserved (cc07ecc06) a logic 0 must be written to these bits. y scalar value (cc05ecc00) these six bits represent the value required to scale the y pixel data from 0.75 to 1.25 of its initial level. the value of these six bits is calculated using the following equation: contrast control register = ( x e0.785) x = scaling factor for y e.g., scale y by 0.9 contrast control register = (0.9e0.75) c/w17 c/w16 c/w15 c/w14 c/w13 c/w12 c/w11 c/w10 c/w15 c/w10 cgms/wss data c/w17 c/w16 cgms data + (, 2<-6a@66 , c/w27 c/w26 c/w25 c/w24 c/w23 c/w22 c/w21 c/w20 c/w27 c/w20 cgms/wss data + ($ 2<-6a@66 $ cc07 cc06 cc05 cc04 cc03 cc02 cc01 cc00 cc05 cc00 y scalar value cc07 cc06 zero should be written to these bits + (% 2 2 adv7172/adv7173 #%3# color control registers 2e1 (cc2ecc1) (address (sr4esr0) = 1ehe1fh) the color control registers are 8-bit-wide registers used to scale the u and v output levels. figure 64 shows the operations under control of these registers. cc1 bit description reserved (cc17ecc16) a logic 0 must be written to these bits. u scalar value (cc15ecc10) these six bits represent the value required to scale the u level from 0.75 to 1.25 of its initial level. the value of these six bits is calculated using the following equation: color control register 1 = ( x e 0.75) x = scaling factor for u e.g., scale u by 0.8 color control register 1 = (0.8 e 0.75) color control register 2 = ( x e 0.75) x = scaling factor for v e.g., scale v by 1.2 color control register 2 = (1.2 e 0.75) hue adjust = (0.17568125 hcr 7 e hcr 0 e 128]). cc17 cc16 cc15 cc14 cc13 cc12 cc11 cc10 cc15 cc10 u scalar value cc17 cc16 zero should be written to these bits cc27 cc26 cc25 cc24 cc23 cc22 cc21 cc20 cc25 cc20 v scalar value cc27 cc26 zero should be written to these bits + (& 2 2 hcr7 hcr6 hcr5 hcr4 hcr3 hcr2 hcr1 hcr0 hcr7 hcr0 hue adjust value + (' 2 adv7172/adv7173 #&4# brightness control registers (bcr) (address (sr5esr0) = 21h) the brightness control register is an 8-bit-wide register which allows brightness control. figure 66 shows the operation under control of this register. bcr bit description reserved (bcr7ebcr5) a logic 0 must be written to these bits. brightness value (bcr4ebcr0) these five bits represent the value required to vary the brightness level or pedestal added to the luma data. the available range is from 0 ire to 7.5 ire in 18 steps. a value of 18 (10010) corre- sponds to 7.5 ire setup level added onto the pixel data. this brightness control is possible in both pal and ntsc. sharpness response register (pr) (address (sr5-sr0) = 22h) the sharpness response register is an 8-bit-wide register. the four msbs are set to 0. the four lsbs are written to in order to select a desired filter response. figure 67 shows the operation under control of this register. pr bit description reserved (pr7epr4) a logic 0 must be written to these bits. sharpness response value (pr3epr0) these four bits are used to select the desired luma filter response. the option of twelve responses is given supporting a gain boost/ attenuation in the range e4 db to +4 db. the value 12 (1100) written to these four bits corresponds to a boost of +4 db while the value 0 (0000) corresponds to e4 db. for normal o pera- tion these four bits are set to 6 (0110). refer to figures 19e21 for filter plots. bcr7 bcr6 bcr5 bcr4 bcr3 bcr2 bcr1 bcr0 bcr4 bcr0 brightness value bcr7 bcr5 zero should be written to these bits + (( 2 pr7 pr6 pr5 pr4 pr3 pr2 pr1 pr0 pr3 pr0 sharpness response value pr7 pr4 zero should be written to these bits + () 6 adv7172/adv7173 #&,# the adv7172/adv7173 is a highly integrated circuit containing both precision analog and high speed digital circuitry. it has been designed to minimize interference effects on the integrity of the analog circuitry by the high speed digital circuitry. it is imperative that these same design and layout techniques be applied to the system level design so that high speed, accurate performance is achieved. the recommended analog circuit l ayout shows the analog interface between the device and monitor. the layout should be optimized for lowest noise on the adv7172/ adv7173 power and ground lines by shielding the digital inputs and providing good decoupling. the lead length between groups of v aa and gnd pins should by minimized to minimize induc- tive ringing. ground planes the ground plane should encompass all adv7172/adv7173 ground pins, voltage reference circuitry, power supply bypass cir- cuitry for the adv7172/adv7173, the analog output traces, and all the digital signal traces leading up to the adv7172/adv 7173. the ground plane is the board?s common ground plane. power planes the adv7172/adv7173, and any associated analog circuitry, should have its own power plane, referred to as the analog power plane (v aa ). this power plane should be connected to the regular pcb power plane (v cc ) at a single point through a ferrite bead. this bead should be located within three inches of the adv7172/adv7173. the metallization gap separating device power plane and board power plane should be as narrow as possible to mini- mize the obstruction to the flow of heat from the device into the general board. the pcb power plane should provide power to all digital logic on the pc board, and the analog power plane should provide power to all adv7172/adv7173 power pins and voltage reference circuitry. plane-to-plane noise coupling can be reduced by ensuring that portions of the regular pcb power and ground planes do not overlay portions of the analog power plane unless they can be arranged so that the plane-to-plane noise is common-mode. supply decoupling for optimum performance, bypass capacitors should be in- stalled using the shortest leads possible, consistent with reliable operation, to reduce the lead inductance. best performance is appendix 1 board design and layout considerations obtained with 0.1 ? adv7172/adv7173 #&$# 0.1 f 5v (v aa ) 23 comp2 35 33 4k 5v (v cc ) 150 21 4k 5v (v cc ) mpu bus 48 44 14 16 15 12, 13, 18, 26, 31, 47 17 20 38 1, 11, 19, 27, 30, 32, 34, 46 0.1 f 0.01 f 5v (v aa ) 10k 5v (v aa ) power supply decoupling for each power supply group 37 gnd alsb hsync field/ vsync blank reset clock r set1 sdata sclock dac a v aa v ref p0 p7 75 75 39 screset/rtc adv7172/ adv7173 unused inputs should be grounded dac b 100 100 5v (v aa ) reset 41 ttx ttxreq 10k 5v (v aa ) ttx ttxreq 0.1 f 36 comp1 43 42 vso clamp pal_ntsc 29 28 dac c 75 300 dac d 25 24 dac e 300 dac f 600 22 r set2 9 2 10 300 45 40 27mhz clock (same clock as used by mpeg2 decoder) cso_hso 4k 4.7 f + (* 2 5 adv7172/adv7173 #&%# the adv7172/adv7173 supports closed captioning, conform- ing to the standard television synchronizing waveform for color transmission. closed captioning is transmitted during the blanked active line time of line 21 of the odd fields and line 284 of even fields. closed captioning consists of a 7-cycle sinusoidal burst that is frequency and phase locked to the caption data. after the clock run-in signal, the blanking level is held for two d ata bits and is followed by a logic level 1 start bit. sixteen b its of data follow the start bit. these consist of two 8-bit bytes, seven data bits and one odd parity bit. the data for these bytes is stored in closed captioning data registers 0 and 1. the adv7172/adv7173 also supports the extended closed captioning operation, which is active during even fields, and is encoded on scan line 284. the data for this operation is stored in closed captioning extended data registers 0 and 1. all clock run-in signals, and timing to support closed capt ion- ing on lines 21 and 284, are automatically generated by the adv7172/adv7173. all pixels inputs are ignored during lines 21 and 284. closed captioning is enabled. appendix 2 closed captioning 12.91 s s t a r t p a r i t y p a r i t y d0 d6 d0 d6 10.003 s 33.764 s 50 ire 40 ire frequency = f sc = 3.579545mhz amplitude = 40 ire reference color burst (9 cycles) 7 cycles of 0.5035 mhz (clock run-in) 10.5 0.25 s two 7-bit + parity ascii characters (data) 27.382 s byte 0 byte 1 + (3 2 2 @ 8!0629 fcc code of federal regulations (cfr) 47 section 15.119 and eia608 describe the closed captioning information for lines 21 and 284. the adv7172/adv7173 uses a single buffering method. this means that the closed captioning buffer is only one byte deep, therefore there will be no frame delay in outputting the closed captioning data, unlike other 2-byte deep buffering systems. the data must be loaded at least one line before (line 20 or line 283) it is outputted on line 21 and line 284. a typical implementation of this method is to use vsync adv7172/adv7173 #&&# the adv7172/adv7173 supports copy generation management system (cgms) conforming to the standard. cgms data is transmitted on line 20 of the odd fields and line 283 of even fields. bits c/w05 and c/w06 control whether or not cgms data is output on odd and even fields. cgms data can only be transmitted when the adv7172/adv7173 is configured in ntsc mode. the cgms data is 20 bits long, the function of each of these bits is as shown below. the cgms data is preceded by a refer - ence pulse of the same amplitude and duration as a cgms bit (see figure 70). these bits are output from the configuration regis ters in the following order: c/w00 = c16, c/w01 = c17, c/w02 = c18, c/w03 = c19, c/w10 = c8, c/w11 = c9, c/w12 = c10, c/w13 = c11, c/w14 = c 12, c/w15 = c13, c/w16 = c14, c/w17 = c15, c/w20 = c0, c/w21 = c1, c/w22 = c2, c/w23 = c3, c/w24 = c4, c/w25 = c5, c/w26 = c6, c/w27 = c7. if the bit c/w04 is set to a logic 1, the last six bits, c19ec14, which comprise the 6-bit crc check sequence, are calcul ated automatically on the adv7172/adv7173 based on the lower 14 bits (c0ec 13) of the data in the data registers and output with the remaining 14 bits to form the complete 20 bits of the cgms data. the calculation of the crc sequence is based on the polynomial x 6 + x + 1 with a preset value of 111111. if c/w04 is set to a logic 0, all 20 bits (c0ec19) are directly output from the cgms registers (no crc calculated, must be calculated by the user) . function of cgms bits word 0 e 6 bits word 1 e 4 bits word 2 e 6 bits crc e 6 bits crc polynomial = x 6 + x + 1 (preset to 111111) word 0 1 0 b1 aspect ratio 16:9 4:3 b2 display format letterbox normal b3 undefined word 0 b4, b5, b6 identification information about video and other signals (e.g., audio) word 1 b7, b8, b9, b10 identification signal incidental to word 0 word 2 b11, b12, b13, b14 identification signal and information incidental to word 0 appendix 3 copy generation management system (cgms) crc sequence 49.1 s 0.5 s 11.2 s 2.235 s 20ns ref c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 c12 c13 c14 c15 c16 c17 c18 c19 100 ire 70 ire 0 ire 40 ire + )4 2<-6@ adv7172/adv7173 #&'# appendix 4 wide screen signaling the adv7172/adv7173 supports wide screen signaling (wss) conforming to the standard. wss data is transmitted on line 23. wss data can only be transmitted when the adv7172/adv7173 is configured in pal mode. the wss data is 14 bits long, the function of each of these bits is as shown below. the wss data is preceded by a run-in sequence and a start code (see figure 71 ). the bits are output from the configuration registers in the following order: c/w20 = w0, c/w21 = w1, c/ w22 = w2, c/w23 = w3, c/w24 = w4, c/w25 = w5, c/w26 = w6, c/w27 = w7, c/w10 = w8, c/w11 = w9, c/w12 = w10, c/w13 = w11, c/w14 = w12, c/w15 = w13. if the bit c/w07 is set to a logic 1 it enables the wss data to be transmitted on line 23. the latter portion of line 23 (42.5 hsync 11.0 s w0 w1 w2 w3 w4 w5 w6 w7 w8 w9 w10 w11 w12 w13 500mv run-in sequence start code active video 38.4 s 42.5 s + ), @66@ b4 0 camera mode 1 film mode b5 0 standard coding 1 motion adaptive color plus b6 0 no helper 1 modulated helper b7 reserved b9 b10 0 0 no open subtitles 1 0 subtitles in active image area 0 1 subtitles out of active image area 1 1 reserved b11 0 no surround sound information 1 surround sound mode b12 reserved b13 reserved adv7172/adv7173 #&(# appendix 5 teletext insertion time, t pd, is the time needed by the adv7172/adv7173 to interpolate input data on ttx and insert it onto the cvbs or y out- puts, such that it appears t synttxout = 10.2 address & data run-in clock teletext vbi line 45 bytes (360 bits) pal + )$ 0 1 5 programmable pulse edges t pd t pd cvbs/y hsync ttxreq ttx data t synttxout = 10.2 s t pd = pipeline delay through adv7172/adv7173 ttx del = ttxreq to ttx (programmable range = 4 bits [0 15 clock cycles]) t synttxout 10.2 s ttx del ttx st + )% 0 1 + adv7172/adv7173 #&)# appendix 6 ntsc waveforms (with pedestal) 130.8 ire 100 ire 7.5 ire 0 ire 40 ire peak composite ref white black level sync level blank level 714.2mv 1268.1mv 1048.4mv 387.6mv 334.2mv 48.3mv + )& !0622 5 100 ire 7.5 ire 0 ire 40 ire ref white black level sync level blank level 714.2mv 1048.4mv 387.6mv 334.2mv 48.3mv + )' !0625 5 650mv 335.2mv 963.8mv 0mv peak chroma blank/black level 286mv (p-p) 629.7mv (p-p) peak chroma + )( !0622 5 100 ire 7.5 ire 0 ire 40 ire ref white black level sync level blank level 720.8mv 1052.2mv 387.5mv 331.4mv 45.9mv + )) !062< 5 adv7172/adv7173 #&*# ntsc waveforms (without pedestal) 130.8 ire 100 ire 0 ire 40 ire peak composite ref white sync level blank/black level 714.2mv 1289.8mv 1052.2mv 338mv 52.1mv + )* !0622 5 100 ire 0 ire 40 ire ref white sync level blank/black level 714.2mv 1052.2mv 338mv 52.1mv + )3 !0625 5 650mv 299.3mv 978mv 0mv peak chroma blank/black level 286mv (p-p) peak chroma 694.9mv (p-p) + *4 !0622 5 100 ire 0 ire 40 ire ref white sync level blank/black level 715.7mv 1052.2mv 336.5mv 51mv + *, !062< 5 adv7172/adv7173 #&3# pal waveforms 1284.2mv 1047.1mv 350.7mv 50.8mv peak composite ref white sync level blank/black level 696.4mv + *$ .52 5 1047mv 350.7mv 50.8mv ref white sync level blank/black level 696.4mv + *% .55 5 650mv 317.2mv 989.7mv 0mv peak chroma blank/black level 300mv (p-p) 672mv (p-p) peak chroma + *& .52 5 1050.2mv 351.8mv 51mv ref white sync level blank/black level 698.4mv + *' .5< 5 adv7172/adv7173 #'4# betacam level 0mv 171mv 334mv 505mv 0mv 171mv 334mv 505mv white yellow cyan green magenta red blue black + *( !062,44b2 ! . /5 betacam level 0mv 158mv 309mv 467mv 0mv 158mv 309mv 467mv white yellow cyan green magenta red blue black + *) !062,44b2 . /5 smpte level 0mv 118mv 232mv 350mv 0mv 118mv 232mv 350mv white yellow cyan green magenta red blue black + ** .5,44b2 /5 uv waveforms betacam level 0mv 82mv 423mv 505mv 0mv 82mv 505mv 423mv white yellow cyan green magenta red blue black + *3 !062,44b2 ! . 5 betacam level 0mv 76mv 391mv 467mv 0mv 76mv 467mv 391mv white yellow cyan green magenta red blue black + 34 !062,44b2 . 5 smpte level 0mv 57mv 293mv 350mv 0mv 57mv 350mv 293mv white yellow cyan green magenta red blue black + 3, .5,44b2 5 adv7172/adv7173 #',# if an output filter is required for the cvbs, y, uv, chroma and rgb outputs of the adv7172/adv7173, the filter shown below can be used. the plot of the filter characteristics is shown in fig ure 93. an output filter is not required if the outputs of the adv7172/adv7173 are connected to most analog monitors or analog tvs; however, if the output signals are applied to a system where sampling is used (e.g., digital tvs), then a filter is required to prevent aliasing. 1.8 h 22pf 270pf 330pf filter i/p filter o/p 75 + 3$ = + / = appendix 7 optional output filter frequency hz 0 40 80 100m 10m 100k magnutude db 10 20 30 50 60 70 1m + 3% = + . appendix 8 optional dac buffering when external buffering is needed of the adv7172/adv7173 dac outputs, the configuration in figure 94 is recommended. this configuration shows the dac outputs, a, b, c, running at half (18 ma) their full current (36 ma) capability. this will allow the adv7172/adv7173 to dissipate less power; the analog current is reduced by 50% with a r set1 = 300 ? ? ? adv7172/adv7173 v ref pixel port v aa output buffer dac a cvbs chroma g luma b r 300 r set1 output buffer dac b output buffer dac c output buffer dac d output buffer dac e output buffer dac f digital core 600 r set2 + 3& = 2 2 dac outputs at 18 ma with a v aa of 3.3 v. this buffer also adds extra isolation on the video outputs (see buffer circuit in figure 95). note that dacs d, e, and f will always require buffering as the full-scale o utput current from these dacs is lim ited to 8.66 ma. with dacs a, b, and c, buffering is optional, based on the user requirements for performance and power consumption. when calculating absolute output full-scale current and voltage, use the following equations: v out = i out r load i out = v ref k () r set k = v ref = ad8051 v cc + v cc 1 5 4 3 2 output to tv monitor input/ optional filter o/p + 3' = 2 adv7172/adv7173 #'$# appendix 9 recommended register values the adv7172/adv7173 registers can be set depending on the user standard required. the following examples give the various register formats for several video standards. in each case the output is set to composite/luma/chroma outputs with dacs d, e and f powered up to provide 8.66 ma and with the blank adv7172/adv7173 #'%# pal m (continued) (f sc = 3.57561149 mhz) address data 12hex closed captioning ext register 1 00hex 13hex closed captioning register 0 00hex 14hex closed captioning register 1 00hex 15hex pedestal control register 0 00hex 16hex pedestal control register 1 00hex 17hex pedestal control register 2 00hex 18hex pedestal control register 3 00hex 19hex cgms_wss reg 0 00hex 1ahex cgms_wss reg 1 00hex 1bhex cgms_wss reg 2 00hex 1chex teletext request control register 00hex 1dhex contrast control register 00hex 1ehex color control register 1 00hex 1fhex color control register 2 00hex 20hex hue control register 00hex 21hex brightness control register 00hex 22hex sharpness control register 00hex pal n (f sc = 4.43361875 mhz) address data 00hex mode register 0 13hex 01hex mode register 1 07hex 02hex mode register 2 68hex 03hex mode register 3 00hex 04hex mode register 4 00hex 05hex mode register 5 00hex 06hex mode register 6 00hex 07hex mode register 7 00hex 0ahex timing register 0 08hex 0bhex timing register 1 00hex 0chex subcarrier frequency register 0 cbhex 0dhex subcarrier frequency register 1 8ahex 0ehex subcarrier frequency register 2 09hex 0fhex subcarrier frequency register 3 2ahex 10hex subcarrier phase register 00hex 11hex closed captioning ext register 0 00hex 12hex closed captioning ext register 1 00hex 13hex closed captioning register 0 00hex 14hex closed captioning register 1 00hex 15hex pedestal control register 0 00hex 16hex pedestal control register 1 00hex 17hex pedestal control register 2 00hex 18hex pedestal control register 3 00hex 19hex cgms_wss reg 0 00hex 1ahex cgms_wss reg 1 00hex 1bhex cgms_wss reg 2 00hex 1chex teletext request control register 00hex 1dhex contrast control register 00hex 1ehex color control register 1 00hex 1fhex color control register 2 00hex 20hex hue control register 00hex 21hex brightness control register 00hex 22hex sharpness control register 00hex pal-60 (f sc = 4.43361875 mhz) address data 00hex mode register 0 12hex 01hex mode register 1 07hex 02hex mode register 2 68hex 03hex mode register 3 00hex 04hex mode register 4 00hex 05hex mode register 5 00hex 06hex mode register 6 00hex 07hex mode register 7 00hex 0ahex timing register 0 08hex 0bhex timing register 1 00hex 0chex subcarrier frequency register 0 cbhex 0dhex subcarrier frequency register 1 8ahex 0ehex subcarrier frequency register 2 09hex 0fhex subcarrier frequency register 3 2ahex 10hex subcarrier phase register 00hex 11hex closed captioning ext register 0 00hex 12hex closed captioning ext register 1 00hex 13hex closed captioning register 0 00hex 14hex closed captioning register 1 00hex 15hex pedestal control register 0 00hex 16hex pedestal control register 1 00hex 17hex pedestal control register 2 00hex 18hex pedestal control register 3 00hex 19hex cgms_wss reg 0 00hex 1ahex cgms_wss reg 1 00hex 1bhex cgms_wss reg 2 00hex 1chex teletext request control register 00hex 1dhex contrast control register 00hex 1ehex color control register 1 00hex 1fhex color control register 2 00hex 20hex hue control register 00hex 21hex brightness control register 00hex 22hex sharpness control register 00hex adv7172/adv7173 #'&# power on reset reg values (pal_ntsc = 0, ntsc selected) address data 00hex mode register 0 00hex 01hex mode register 1 07hex 02hex mode register 2 08hex 03hex mode register 3 00hex 04hex mode register 4 00hex 05hex mode register 5 00hex 06hex mode register 6 00hex 07hex mode register 7 00hex 0ahex timing register 0 00hex 0bhex timing register 1 00hex 0chex subcarrier frequency register 0 16hex 0dhex subcarrier frequency register 1 7chex 0ehex subcarrier frequency register 2 f0hex 0fhex subcarrier frequency register 3 21hex 10hex subcarrier phase register 00hex 11hex closed captioning ext register 0 00hex 12hex closed captioning ext register 1 00hex 13hex closed captioning register 0 00hex 14hex closed captioning register 1 00hex 15hex pedestal control register 0 00hex 16hex pedestal control register 1 00hex 17hex pedestal control register 2 00hex 18hex pedestal control register 3 00hex 19hex cgms_wss reg 0 00hex 1ahex cgms_wss reg 1 00hex 1bhex cgms_wss reg 2 00hex 1chex teletext request control register 00hex 1dhex contrast control register 00hex 1ehex color control register 1 00hex 1fhex color control register 2 00hex 20hex hue control register 00hex 21hex brightness control register 00hex 22hex sharpness control register 00hex power on reset reg values (pal_ntsc = 1, pal selected) address data 00hex mode register 0 00hex 01hex mode register 1 07hex 02hex mode register 2 08hex 03hex mode register 3 00hex 04hex mode register 4 00hex 05hex mode register 5 00hex 06hex mode register 6 00hex 07hex mode register 7 00hex 0ahex timing register 0 00hex 0bhex timing register 1 00hex 0chex subcarrier frequency register 0 cbhex 0dhex subcarrier frequency register 1 8ahex 0ehex subcarrier frequency register 2 09hex 0fhex subcarrier frequency register 3 2ahex 10hex subcarrier phase register 00hex 11hex closed captioning ext register 0 00hex 12hex closed captioning ext register 1 00hex 13hex closed captioning register 0 00hex 14hex closed captioning register 1 00hex 15hex pedestal control register 0 00hex 16hex pedestal control register 1 00hex 17hex pedestal control register 2 00hex 18hex pedestal control register 3 00hex 19hex cgms_wss reg 0 00hex 1ahex cgms_wss reg 1 00hex 1bhex cgms_wss reg 2 00hex 1chex teletext request control register 00hex 1dhex contrast control register 00hex 1ehex color control register 1 00hex 1fhex color control register 2 00hex 20hex hue control register 00hex 21hex brightness control register 00hex 22hex sharpness control register 00hex adv7172/adv7173 #''# appendix 10 optional dac buffering 0.6 0.4 0.2 0.0 0.2 l608 0.0 10.0 20.0 30.0 40.0 50.0 60.0 microseconds noise reduction: 0.00 db apl = 39.1% precision mode off sound-in-sync off 625 line pal no filtering synchronous sync = source slow clamp to 0.00 v at 6.72 s frames selected: 1 2 3 4 volts + 3( ,44>4>)'>4.52 microseconds apl needs sync = source! precision mode off sound-in-sync off 625 line pal no filtering synchronous sync = a slow clamp to 0.00 v at 6.72 s frames selected: 1 0.5 0.0 l575 0.0 10.0 20.0 30.0 40.0 50.0 60.0 70.0 volts + 3) ,44>4>)'>4.52 5 adv7172/adv7173 #'(# apl needs sync = source! precision mode off sound-in-sync off 625 line pal no filtering synchronous sync = a slow clamp to 0.00 v at 6.72 s frames selected: 1 0.5 0.0 0.5 10.0 30.0 40.0 50.0 60.0 20.0 microseconds l575 volts no bruch signal + 3* ,44>4>)'>4.52 2 apl = 44.6% precision mode off 525 line ntsc no filtering synchronous sync = a slow clamp to 0.00 v at 6.72 s frames selected: 1 2 microseconds 0.5 0.0 50.0 50.0 100.0 ire:flt volts f1 l76 0.0 10.0 20.0 30.0 40.0 50.0 60.0 0.0 + 33 ,44>)'>)'>)'!0622 adv7172/adv7173 #')# noise reduction: 15.05db apl = 44.7% precision mode off 525 line ntsc no filtering synchronous sync = source slow clamp to 0.00 v at 6.72 s frames selected: 1 2 microseconds 10.0 20.0 30.0 40.0 50.0 60.0 0.6 0.4 0.2 0.0 0.2 50.0 0.0 ire:flt volts f2 l238 + ,44 ,44>)'>)'>)'!0622 5 noise reduction: 15.05db apl needs sync = source! precision mode off 525 line ntsc no filtering synchronous sync = b slow clamp to 0.00 v at 6.72 s frames selected: 1 2 microseconds 0.0 10.0 20.0 30.0 40.0 50.0 60.0 0.4 0.2 0.0 0.2 0.4 volts 50.0 50.0 f1 l76 ire:flt + ,4, ,44>)'>)'>)'!0622 2 adv7172/adv7173 #'*# apl = 39.6% sound in sync off v u yi yl g r m g cy m g cy g r 75% 100% b b system line l608 angle (deg) 0.0 gain 1.000 0.000db 625 line pal burst from source display +v & v + ,4$ .5 . apl = 45.1% setup 7.5% r-y b-y yi g cy m g cy i r 75% 100% b b system line l76f1 angle (deg) 0.0 gain 1.000 0.000db 525 line ntsc burst from source q q i + ,4% !062 . adv7172/adv7173 #'3# outline dimensions dimensions shown in inches and (mm). 48-lead lqfp (st-48) 0.354 (9.00) bsc 0.276 (7.0) bsc 1 12 13 25 24 36 37 48 top view (pins down) 0.276 (7.0) bsc 0.354 (9.00) bsc 0.011 (0.27) 0.006 (0.17) 0.019 (0.5) bsc seating plane 0.063 (1.60) max 0 min 0 7 0.006 (0.15) 0.002 (0.05) 0.030 (0.75) 0.018 (0.45) 0.057 (1.45) 0.053 (1.35) 0.030 (0.75) 0.018 (0.45) 0.007 (0.18) 0.004 (0.09) #(4# 244$$$ #4#&>4,89 .!0!/6 |
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